As the integrated circuit manufacturing technology advances, device feature sizes shrink and the number of transistors that can be integrated on a single die grows exponentially. Associated with the decreasing feature sizes are benefits as well as complexities. Some of the complexities are related to breakdown in reversed bias junctions at sufficiently high voltages. For example, programming some memory devices currently involves high voltages which may exceed the breakdown voltage of gate-drain junction of MOS transistors.
The breakdown may result in a damaging leakage current passing through the device when the device is expected to be in non-conducting (OFF) state. The breakdown effect is deemed to be exacerbated as the feature sizes decrease, even when the applied high voltages are unchanged.